Driver circuits for supplying drive voltage and current to an electrical load like a loudspeaker or a motor are known in the art. These driver circuits are coupled to a pair of power supply voltages to deliver signal or d125 ive power to the electrical load for example in form of audio signals. An H-bridge driver is a popular type of driver circuit which comprises two essentially identical drivers or half-bridges—denoted a left half-bridge and a right half-bridge. In each half-bridge, an upper leg or upper section comprises one or more semiconductor switches coupled to the positive power supply voltage while another leg is coupled to the negative power supply voltage and is designated a lower leg or section. A circuit node established in-between the upper and lower legs is designated a driver output to which the electrical load or load is operatively connectable. By selecting an appropriate timing scheme of control signals applied to respective control inputs of the semiconductor switches of the upper and lower legs of the driver circuit, the driver output toggles between at least two output states to create AC signal voltage swing across the load.
A semiconductor switch comprises at least one control terminal or input and two switch terminals between which an electrical resistance can be controlled in response to a control signal at the control input. When a semiconductor switch is in an ‘on state’ or ‘closed state’ a resistance between the two switch terminals is a relatively low while the resistance is relatively high (relative to the closed state) when the switch is in its ‘off state’ or ‘open state’ or simply off.
The respective control signals may be generated by an appropriate control circuit. For instance when the driver circuit is utilized as a load driver in a class-D amplifier, the respective control signals are usually of the digital type, turning the semiconductor switches either fully on, i.e. in a closed state, or fully off, i.e. in an open state; naturally, with a short transition period in between. Several functional variants of H-bridge drivers are known in the art, for example having two or three output states and one transitional state. In a two state H-bridge driver, output states of each driver output is toggled between the positive and negative power supply voltage in accordance with a particular drive signal. The drive signal may be PWM or PDM modulated drive signal. In a three state, or three level, H-bridge driver, output states of the pair of driver outputs may be toggled between the positive power supply voltage, the negative supply voltage and an high-impedance state/tristate or a zero-state where both driver outputs are pulled to the positive supply voltage or both pulled to the negative supply voltage.
In traditional driver circuits, a short time interval of so-called blanking time has often been introduced in connection with a state transition of the driver output. During the blanking time a semiconductor switch of the upper leg and a semiconductor switch of the lower leg are both placed in respective open states. During the blanking time, the load floats relative to the power supply voltages. This means the driver output, and consequently the load, is not actively pulled towards one of the power supply voltages due to the open states of the upper and lower legs.
The blanking time is introduced to avoid unnecessary power dissipation in the semiconductor switches of the upper and lower legs by short-circuiting the power supply directly by a current path formed through the upper leg and the lower leg. In absence of the blanking time, semiconductor process variations and temperature dependent variations in the relative timing between control signals driving the semiconductor switches of the upper leg and the control signals driving the semiconductor switch of the lower leg can form an unintended state where the respective semiconductor switches of the upper and lower legs are simultaneously closed.
This short-circuiting of the power supply during an unintended overlap state will often lead to significant power dissipation because the respective on-resistances of the semiconductor switches of the upper and the lower legs in their closed states are very low. The low on-resistance is on the other hand necessary, or at least advantageous, because electrical characteristics of the load in combination with the electrical characteristics of the semiconductor switches play an important role for the performance of the driver circuit. The upper and lower legs are designed with on-resistances that are much smaller than an ohmic resistance of the load such that output signal power primarily is dissipated in the load and only to a much smaller extent dissipated in the semiconductor switch(es) as power loss.
Typically, the on-resistance in a leg of a driver circuit designed for driving a 4-8 Ohms loudspeaker load is set to value in a range between of 0.1 and 0.5 Ohms depending on a desired efficiency. Typically, the off-resistance of the upper or lower leg is very large; that is, in order of MΩ or GΩ.
Generally, the load has an impedance that can be modelled with a network of ohmic, inductive and capacitive components. Load impedances presented by components such as loudspeakers and motors are dominated by an inductive behaviour and ohmic resistance.
Two square-wave drive signals at a predetermined switching frequency are conventionally applied as respective control signals to drive the upper and lower legs of the driver. When the switching frequency of the square-wave drive signal is relatively high compared to an inverse time constant of the load and the load impedance has a significant inductive component, the driver will change the load current in small quanta for each period of the switching frequency.
This fact leads to a number of unsolved problems in the previously described traditional driver circuits, including H-bridge drivers that utilize blanking time in connection with a state transition of a driver output. Immediately before the blanking period or time begins, load current in an H-bridge driver is flowing through the load either from left to right or vice versa in because the semiconductor switches are in their closed states to supply load current/power to the load. The path where this load current is flowing is subsequently abruptly opened or disconnected when the respective semiconductor switches are set to their respective open states in connection with the start of the blanking period. Thus, immediately after the blanking time has begun, the load current continues to flow as immediately before the start of the blanking time because the inductive component of the load attempts to retain the flow of load current despite the respective semiconductor switches of the upper and lower legs being opened or off. In turn, large voltage spikes are generated across the load and these tend to stress the semiconductor switches and degrade their reliability.
Furthermore, in case the semiconductor switches of the driver are implemented as CMOS transistors a parasitic diode junction is inevitably established when such a load current supplied out of a drain terminal of a NMOS/PMOS transistor or into a drain terminal of the NMOS/PMOS transistor. Depending on a direction of the load current immediately before start of the blanking time, a voltage spike is generated either across a parasitic substrate diode of the lower CMOS transistor or across a parasitic substrate diode of the upper CMOS transistor. This voltage spike will shift the voltage on the driver output to a level either above the positive power supply voltage or a level below the negative power supply voltage.
Thus for CMOS based driver circuits, the disruption of an established flow of load current in connection with the blanking time causes the parasitic substrate diode between the transistors' source and drain terminal to conduct and induce a voltage drop across the parasitic substrate diode. This voltage drop will shift the voltage level at the driver output connected to the load to a potential approximately 0.7 Volts above the positive supply (assuming that ohmic resistance associated with the parasitic diode is negligible). Alternatively, this voltage drop will shift the voltage level at the driver output to a potential approximately 0.7 Volts below the negative supply. For several reasons this is undesired. Since disrupting the loop where load current is flowing through an inductive impedance, a substantial voltage spike or peak is generated. Such voltage spikes will occur every time the respective semiconductor switch of an upper and a lower leg are opened simultaneously. This phenomenon causes Electromagnetic Interference (EMI) noise because the voltage spikes are superimposed on the power supply voltages or rails. Further, an excessive amount of power is dissipated in the semiconductor switches due to the voltage spikes caused by the substrate currents. This reduces efficiency of the driver circuit. In addition CMOS transistors are not designed for conducting such substrate currents through the associated parasitic diode so this may stress the CMOS transistors, i.e. semiconductor switches, and degrade their reliability.
Another problem associated with the above-discussed the voltage spikes is that the power supply voltage to the driver circuit must be set to a lower DC voltage than otherwise possible to ensure compliance with absolute maximum voltage ratings of the semiconductor process in question taking the voltage spikes into account. The lowered DC voltage to the driver circuit is a safety margin needed due to the expected power supply voltage overshoots or undershoots. Since the maximum load signal voltage and thus signal power in the load is approximately proportional to the power supply voltage raised to a power of two, the required safety margin significantly limits the maximum output power of the driver circuit.
Finally, in numerous applications it is desirable to generate an analogue signal voltage with low distortion across the load. Such analogue signals are often generated by letting an inductive component of a load impedance act as a low-pass filter on a Class-D modulated driver output signal to attenuate switching frequency components remaining from the switching frequency of the class-D modulation. In this type of application, the voltage spikes caused by the disruption of the current patent during the blanking time may introduce a substantial amount of distortion in the analogue signal voltage across the load.